A Highly Linear and Efficient CMOS Power Amplifier With Cascode–Cascade Configuration

This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode–cascade configuration. The proposed configuration improves AM–PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier. In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off. The PA is implemented in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process with an output combining network in printed circuit board. It provides an average power of 24.5 dBm with a PAE of 45.6% for a long-term-evolution 10-MHz up-link signal with the ACLR_E–UTRA of −30 dBc at 2 GHz.