Heterogeneous Integration Hybrid Substrate with Ajinomoto Build-Up Film

The design, materials, process, and fabrication of a hybrid substrate for the heterogeneous integration of chips with 50μm-pitch (minimum) by fan-out chip-last panel-level packaging are presented. The hybrid substrate consists of a fine metal linewidth (L), spacing (S), and thickness (H) RDL (redistribution-layer) substrate, solder joints with underfill, and a build-up package substrate. The dielectric material for the fine metal L/S/H RDL-substrate is an Ajinomoto build-up film (ABF).

[1]  Wei-Jie Yin,et al.  Mechanical and Thermal Characterization Analysis of Chip-last Fan-out Chip on Substrate , 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

[2]  Chen-Chao Wang,et al.  Advanced Fanout Packaging Technology for Hybrid Substrate Integration , 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

[3]  Shu-Han Yang,et al.  Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration , 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

[4]  J. Lau,et al.  Hybrid Substrate by Fan-Out RDL-First Panel-Level Packaging , 2021, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[5]  J. Lau,et al.  Fan-Out (RDL-First) Panel-Level Hybrid Substrate for Heterogeneous Integration , 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

[6]  Seok Won Lee,et al.  Cost Effective 2.3D Packaging Solution by using Fanout Panel Level RDL , 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

[7]  J. Lau.  State of the Art of Lead-Free Solder Joint Reliability , 2021 .

[8]  K. Oi,et al.  Electro-migration evaluation between organic interposer and build-up substrate on 2.3D organic package , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[9]  Wei-Hong Lai,et al.  A Comparative Study of 2.5D and Fan-out Chip on Substrate : Chip First and Chip Last , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[10]  K. Oi,et al.  Development of 2.3D High Density Organic Package using Low Temperature Bonding Process with Sn-Bi Solder , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[11]  C.S. Chen,et al.  Multilayer RDL Interposer for Heterogeneous Device and Module Integration , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[12]  Chen-Chao Wang,et al.  Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[13]  Dan Oh,et al.  Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).