论文信息 - A 2.0 micron BiCMOS process including DMOS transistors for merged linear ASIC analog/digital/power applications

A 2.0 micron BiCMOS process including DMOS transistors for merged linear ASIC analog/digital/power applications

A 2.0 mu m BiCMOS process incorporating 30 V bipolar, 5-50 V CMOS, precision analog elements, and 45 V power DMOS transistors with 2.0 m Omega cm/sup 2/ R/sub DSON/ area is presented. The process is compatible with a mature mixed-signal application-specific integrated circuit (ASIC) cell library and offers fully isolated CMOS devices, providing an effective solution for intelligent analog/digital/power applications with inductive loads. This technology has been applied to the design of a 2.5 A H-bridge with supporting logic and analog control circuitry.<<ETX>>

John P. Erdeljac | Louis N. Hutter | B. Todd | Konrad Wagensohner | Walter Bucksch

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