7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate

In recent years, the explosive growth of handheld smart devices has demanded increasing network capacity and higher data-rate. With around 1GHz bandwidth in the 5GHz UNII frequency band, 802.11ac offers great flexibility in utilizing a wider signal bandwidth and more complex modulation scheme to achieve the PHY rate up to 1.733Gb/s with VHT160 2×2 MIMO. The increased signal bandwidth from 80MHz (Stage1) to 160MHz (Stage2) poses stringent design challenges for radio transceivers, such as tighter frequency synthesizer phase-noise requirement for better EVM floor, techniques of using integrated high-power PAs for achieving 160MHz operation, and overcoming the effect of LPF 3dB-corner-mismatch-induced Frequency-Dependent IQ imbalance (FD-IQ) [1] due to finite OP-Amp Gain-BW product and submicron process gradient effect. This paper describes a monolithic MIMO 802.11ac Stage-2 Wi-Fi SoC chip with integrated dual-band PA's, LNA's, and T/R switches.

[1]  Chun-Wei Lin,et al.  Dual-band integrated Wi-Fi PAs with load-line adjustment and phase compensated power detector , 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[2]  Pi-An Wu,et al.  A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS , 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

[3]  Li Lin,et al.  20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).