Asynchronous logiс one-level LUT design based on partial acknowledgement

Abstract In the paper, asynchronous logic design targeting LUT of custom size (number of inputs) implementation is proposed. It is based on conventional Sum-Of-Product terms (SOP) what differs from existing methods where Sum-Of-Minterms (SOM) and Disjoint SOP are supposed. It is shown, that LUT architectural features and delays ensure SOP hazard-free implementation. Nowadays reconfigurable chips contain multiple LUTs that can be combined using so called dedicated multiplexers. It implies producing LUT-based structure of various inputs number to match design needs. As a result, a function can be implemented using one-level LUT which increases the circuit performance. It is in contrast to the conventional approach where multi-level implementation is supposed. The model consists of functional and completion detection (CD) blocks. Both blocks are implemented using LUTs. LUTs total size is an optimization criterion. The method of LUTs total size minimization is proposed where inputs are removed from CD block and partially acknowledged via functional one. The problem is formulated as a covering task. Two sets of benchmarks are processed and comparison is done. Using our method, improvement w.r.t mention criterion is achieved.

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