A 2500 gate programmable logic device with subdivisable macrocells

A 2500-gate programmable logic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standard third-party software tools. Global routing and subdivisable macrocells provide gate utilization factors equivalent to gate arrays.<<ETX>>