Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation

[1]  Mani Soma,et al.  Analytical fault modeling and static test generation for analog ICs , 1994, ICCAD.

[2]  Hans G. Kerkhoff,et al.  Fast fault simulation for nonlinear analog circuits , 2003, IEEE Design & Test of Computers.

[3]  C.-J. Richard Shi,et al.  Rapid frequency-domain analog fault simulation under parameter tolerances , 1997, DAC.

[4]  Anil Pahwa,et al.  Band faults: Efficient approximations to fault bands for the simulation before fault diagnosis of linear circuits , 1982 .

[5]  Ronald S. Gyurcsik,et al.  Optimal ordering of analog integrated circuit tests to minimize test time , 1991, 28th ACM/IEEE Design Automation Conference.

[6]  Abhijit Chatterjee,et al.  DC Built-In Self-Test for Linear Analog Circuits , 1996, IEEE Des. Test Comput..

[7]  C.-J. Richard Shi,et al.  Nonlinear analog DC fault simulation by one-step relaxation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[8]  Jaijeet S. Roychowdhury,et al.  Homotopy techniques for obtaining a DC solution of large-scale MOS circuits , 1996, DAC '96.

[9]  Yin Shi,et al.  Accelerated techniques in stem fault simulation , 2008, Journal of Computer Science and Technology.

[10]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Abhijit Chatterjee,et al.  Concurrent transient fault simulation for analog circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Michael J. Ohletz Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[13]  Manoj Sachdev,et al.  Industrial relevance of analog IFA: a fact or a fiction , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[14]  P. R. Menon,et al.  Fault simulation , 1986 .

[15]  C.-J.R. Shi,et al.  Efficient DC fault simulation of nonlinear analog circuits , 1998, Proceedings Design, Automation and Test in Europe.

[16]  Mark Zwolinski,et al.  Concurrent analogue fault simulation , 1997 .

[17]  A. Householder A Survey of Some Closed Methods for Inverting Matrices , 1957 .

[18]  James M. Ortega,et al.  Iterative solution of nonlinear equations in several variables , 2014, Computer science and applied mathematics.

[19]  Abhijit Chatterjee,et al.  Fault simulation of linear analog circuits , 1993, J. Electron. Test..