Modular operational semantic specification of transport triggered architectures

The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult. However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and the specification can be animated, providing a simulator. This paper proposes a high level structural operational semantic (S.O.S.) specification for the class of transport triggered architectures. These architectures are simple, powerful, flexible and modular and can exploit very fine grained parallelism. The S.O.S. is novel in that it follows the structure of the architecture, and by doing so inherits the modularity of the architecture.

[1]  Alexandru Nicolau,et al.  Parallel processing: a smart compiler and a dumb machine , 1984, SIGP.

[2]  Henk Corporaal,et al.  Move32int, a sea of gates realization of a high performance transport triggered architecture , 1993, Microprocess. Microprogramming.

[3]  Robert S. Boyer,et al.  Automated proofs of object code for a widely used microprocessor , 1996, JACM.

[4]  Henk Corporaal,et al.  Code generation for transport triggered architectures , 1994, Code Generation for Embedded Processors.

[5]  Bishop Brock,et al.  The Verification of a Bit-slice ALU , 1989, Hardware Specification, Verification and Synthesis.

[6]  Bill Roscoe,et al.  An Operational Semantics for CSP , 1986 .

[7]  Miriam Leeser,et al.  HML: A Hardware Description Language Based on Standard ML , 1993, CHDL.

[8]  John T. O'Donnell,et al.  Generating Netlists from Executable Circuit Specifications , 1992, Functional Programming.

[9]  WadlerPhilip,et al.  Report on the programming language Haskell , 1992 .

[10]  Alex Aiken,et al.  Compaction-Based Parallelization , 1988 .

[11]  Henk Corporaal,et al.  MOVE: a framework for high-performance processor design , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[12]  John Launchbury,et al.  Functional Programming, Glasgow 1992 , 1993, Workshops in Computing.

[13]  John Hannan.  Operational semantics-directed compilers and machine architectures , 1994, TOPL.

[14]  Henk Corporaal.  Transport Triggered Architectures : Design and Evaluation , 1995 .

[15]  George C. Necula,et al.  Safe kernel extensions without run-time checking , 1996, OSDI '96.