Design and performance of micron-size devices

Abstract Taking drain-area breakdown and punch-through as fundamental limitations for small devices, several design aspects are discussed for miniaturizing MOS- and I 2 L gates. From these limitations unique relations are derived for relevant device-design parameters and dimensions. According to these criteria-designed gates the delay time and the speed-power product have been computed as a function of device dimensions. A number of results are compared with available experimental data. Although the improvement of switching speed in smaller structures is much better for MOS-gates than for I 2 L-gates, the latter gate still maintains some speed advantage for dimensions above 2 ωm.