Using Synthesis Techniques in SAT Solvers

In many application domains in VLSI CAD, like formal verification or test pattern generation, the problem to be solved can be formulated as an instance of satisfiability (SAT). The SAT instance in this cases is usually derived from a circuit description. In this paper we propose to use techniques known from logic synthesis to speed up SAT solvers. By experiments it is shown that these techniques are orthotogonal, i.e. SAT instances can be simplified by logic synthesis approaches and by this are solved much faster. As a case study the techniques are applied to integer factorization – a class of problems that is known to be hard for SAT solvers. Experiments show that improvements of several orders of magnitude can be observed.

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