A Dual-VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation

In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement

[1]  Tadahiro Kuroda,et al.  Utilizing surplus timing for power reduction , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[2]  David G. Chinnery,et al.  Linear programming for sizing, Vth and Vdd assignment , 2005, ISLPED '05.

[3]  Kimiyoshi Usami,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1998 .

[4]  Noel Menezes,et al.  The scaling challenge: can correct-by-construction design help? , 2003, ISPD '03.

[5]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[6]  M. Khellah,et al.  Static pulsed bus for on-chip interconnects , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[7]  Dennis Sylvester,et al.  A new algorithm for improved VDD assignment in low power dual VDD systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[8]  Himanshu Kaul,et al.  A novel buffer circuit for energy efficient signaling in dual-VDD systems , 2005, ACM Great Lakes Symposium on VLSI.

[9]  Ankur Srivastava,et al.  On gate level power optimization using dual-supply voltages , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[10]  M. Hamada,et al.  Low-power CMOS digital design with dual embedded adaptive power supplies , 2000, IEEE Journal of Solid-State Circuits.

[11]  H. Momose,et al.  A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[12]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.