Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes
暂无分享,去创建一个
[1] Valentin Savin,et al. Min-Max decoding for non binary LDPC codes , 2008, 2008 IEEE International Symposium on Information Theory.
[2] Xiaoheng Chen,et al. High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Tong Zhang,et al. Area-Efficient Min-Sum Decoder Design for High-Rate Quasi-Cyclic Low-Density Parity-Check Codes in Magnetic Recording , 2007, IEEE Transactions on Magnetics.
[4] D. Declercq,et al. Fast Decoding Algorithm for LDPC over GF(2q) , 2003 .
[5] Zhongfeng Wang,et al. Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[6] Henk Wymeersch,et al. Log-domain decoding of LDPC codes over GF(q) , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).
[7] D. Mackay,et al. Low density parity check codes over GF(q) , 1998, 1998 Information Theory Workshop (Cat. No.98EX131).
[8] Qin Huang,et al. Array dispersions of matrices and constructions of quasi-cyclic LDPC codes over non-binary fields , 2008, 2008 IEEE International Symposium on Information Theory.
[9] C. Spagnol,et al. Hardware Implementation of ${\rm GF}(2^{m})$ LDPC Decoders , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[10] C. Spagnol,et al. Hardware Implementation of LDPC Decoders , 2009 .
[11] David Declercq,et al. Decoding Algorithms for Nonbinary LDPC Codes Over GF$(q)$ , 2007, IEEE Transactions on Communications.
[12] M. Fossorier,et al. Architecture of a low-complexity non-binary LDPC decoder for high order fields , 2007, 2007 International Symposium on Communications and Information Technologies.
[13] Qin Huang,et al. Quasi-cyclic LDPC codes: an algebraic construction , 2010, IEEE Transactions on Communications.
[14] D. Mackay,et al. Low-Density Parity Check Codes over , 1998 .
[15] Xinmiao Zhang,et al. Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes , 2010, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing.
[16] Shu Lin,et al. Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[17] Fang Cai,et al. Architecture for Non-binary LDPC Decoding , 2011 .
[18] Zhongfeng Wang,et al. An Efficient VLSI Architecture for Nonbinary LDPC Decoders , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.