The CMOS carry-forward adders

The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-/spl mu/m CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm/sup 2/ silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps.

[1]  Graham A. Jullien,et al.  Fast adders using enhanced multiple-output domino logic , 1997 .

[2]  H. Suzuki,et al.  A 64 bit carry look-ahead CMOS adder using Modified Carry Select , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[3]  D. L. Stasiak,et al.  A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology , 2001 .

[4]  Ravi Kumar Kolagotla,et al.  A 1.0-nsec 32-bit prefix tree adder in 0.25-/spl mu/m static CMOS , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[5]  Hoi-Jun Yoo,et al.  Race logic architecture (RALA): a novel logic concept using the race scheme of input variables , 2002 .

[6]  Chung-Hsun Huang,et al.  Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques , 2002 .

[7]  C. M. Lee,et al.  High-speed compact circuits with CMOS , 1982 .

[8]  George D. Gristede,et al.  Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability , 1999, IEEE J. Solid State Circuits.

[9]  Chingwei Yeh,et al.  Fast and compact dynamic ripple carry adder design , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[10]  G. A. Ruiz,et al.  Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits , 1998 .

[11]  A. Inoue,et al.  A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[12]  Makoto Suzuki,et al.  A 1.5-ns 32-b CMOS ALU in double pass-transistor logic , 1993 .

[13]  S.H. Dhong,et al.  470 ps 64-bit parallel binary adder [for CPU chip] , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).