A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 /spl mu/m, and via etch through the required material stack.

[1]  A. Fan,et al.  Copper Wafer Bonding , 1999 .

[2]  K. W. Lee,et al.  Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[3]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  P. Ramm,et al.  InterChip via technology for vertical system integration , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[5]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[6]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[7]  Russell P. Kraft,et al.  Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).