Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach.

[1]  Wayne Luk,et al.  Wordlength optimization for linear digital signal processing , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Wayne Luk,et al.  Optimal datapath allocation for multiple-wordlength systems , 2000 .

[3]  Scott A. Mahlke,et al.  Bitwidth cognizant architecture synthesis of custom hardwareaccelerators , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  SungWonyong,et al.  Combined word-length optimization and high-level synthesis of digital signal processing systems , 2006 .

[5]  Alice C. Parker,et al.  Accuracy sensitive word-length selection for algorithm optimization , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[6]  W. Luk,et al.  Truncation noise in fixed-point SFGs [digital filters] , 1999 .

[7]  Peter Marwedel,et al.  OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming , 1994, EURO-DAC '94.

[8]  Wayne Luk,et al.  Heuristic datapath allocation for multiple wordlength systems , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Wonyong Sung,et al.  Combined word-length optimization and high-level synthesis ofdigital signal processing systems , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Octavio Nieto-Taladriz,et al.  Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach , 2004, 2004 12th European Signal Processing Conference.

[11]  W. Luk,et al.  Truncation noise in fixed-point SFGs , 1999 .

[12]  Patrick Schaumont,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, DATE '99.

[13]  Nikil D. Dutt,et al.  A unified lower bound estimation technique for high-level synthesis , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Wayne Luk,et al.  The Multiple Wordlength Paradigm , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[15]  Octavio Nieto-Taladriz,et al.  Bit-width selection for data-path implementations , 1999, Proceedings 12th International Symposium on System Synthesis.

[16]  Sun-Young Hwang,et al.  Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design , 1996 .

[17]  G. Nemhauser,et al.  Integer Programming , 2020 .

[18]  George A. Constantinides Perturbation analysis for word-length optimization , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..