Low power D flip-flop serial in/parallel out based shift register

The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design. The flip-flops (FF's) consumption of casual logic power in a SoC chip (system on chip) commonly overpasses 50% as long the input and the output are in the same state thanks to the redundancy transition of interior loops. Conventional implementation of shift register systems such as linear feedback shift registers (LFSR) have two main drawbacks namely that elements into structure have been clocked during every clock cycle, and throughput is confined to just one (1) bit per clock cycle. Large scale integrated systems have much higher power consumption when tested due to the increased level of circuit activity. The higher rate of circuit activity can help reduce transition times that are from the input to the output phases. Flip-flops have been performed in 0.18μm CMOS technology. Circuit simulations with displays showing appropriate power dissipations have been reduced are possible where input signals decrease switching activities. A 16-Bit shift register is shown as an easy low power usage.

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