Impact of irregular geometries on low-k dielectric breakdown

Backend geometries on chips contain a wide variety of features. We are developing a full-chip reliability simulator for low-k dielectric breakdown that takes into account the vulnerable area, linewidth, vias, and line edge roughness. The simulator provides a link between test structure results and predictions of chip dielectric lifetime. However, these factors may not be sufficient for large chips with a wider variety of features. In this paper, we analyze data from backend dielectric test structures with irregular geometries to determine if more layout features need to be added to a full-chip reliability simulator for low-k dielectric breakdown.

[1]  Atsuko Yamaguchi,et al.  Characterization of Line-edge Roughness in Cu/low-k Interconnect Pattern , 2007 .

[2]  Sung Kyu Lim,et al.  Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown , 2010, Microelectron. Reliab..

[3]  Linda Milor,et al.  Backend low-k TDDB chip reliability simulator , 2011, 2011 International Reliability Physics Symposium.

[4]  A. S. Oates,et al.  Limitation of Low-k Reliability due to Dielectric Breakdown at Vias , 2008, 2008 International Interconnect Technology Conference.

[5]  Linda S. Milor,et al.  A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation , 2009, Microelectron. Reliab..

[6]  Suzumura Naohito,et al.  A NEW TDDB DEGRADATION MODEL BASED ON CU ION DRIFT IN CU INTERCONNECT DIELECTRICS , 2007 .

[7]  P.R. Chidambaram,et al.  Pattern Based Prediction for Plasma Etch , 2007, IEEE Transactions on Semiconductor Manufacturing.

[8]  J. McPherson,et al.  Acceleration Factors for Thin Gate Oxide Stressing , 1985, 23rd International Reliability Physics Symposium.

[9]  Andrzej J. Strojwas,et al.  Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Linda S. Milor,et al.  Analysis of the layout impact on electric fields in interconnect structures using finite element method , 2004, Microelectron. Reliab..

[11]  J. Schneider,et al.  Practical aspects of reliability analysis for IC designs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  Linda Milor,et al.  Analysis of the impact of linewidth variation on low-k dielectric breakdown , 2010, 2010 IEEE International Reliability Physics Symposium.

[13]  T. Sullivan,et al.  A Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[14]  Atsuko Yamaguchi,et al.  Characterization of line-edge roughness in Cu/low-k interconnect pattern , 2007, SPIE Advanced Lithography.

[15]  C. W. Jurgensen,et al.  Microscopic uniformity in plasma etching , 1992 .