Towards compositionality in execution time analysis: definition and challenges
暂无分享,去创建一个
[1] Jan Reineke,et al. Sound and Efficient WCET Analysis in the Presence of Timing Anomalies , 2009, WCET.
[2] Frank Mueller,et al. Languages, Compilers, and Tools for Embedded Systems , 1998, Lecture Notes in Computer Science.
[3] Robert I. Davis,et al. Cache Related Pre-emption Delay Aware Response Time Analysis for Fixed Priority Pre-emptive Systems , 2011, RTSS.
[4] Jan Reineke,et al. Impact of resource sharing on performance and performance prediction , 2013, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[5] Reinhard Wilhelm,et al. Cache Behavior Prediction by Abstract Interpretation , 1996, Sci. Comput. Program..
[6] Lili Tan,et al. The worst-case execution time tool challenge 2006 , 2006, Second International Symposium on Leveraging Applications of Formal Methods, Verification and Validation (isola 2006).
[7] Sebastian Altmeyer,et al. Resilience analysis: tightening the CRPD bound for set-associative caches , 2010, LCTES '10.
[8] Ashkan Beyranvand Nejad,et al. Virtual execution platforms for mixed-time-criticality applications : the CompSoC architecture and design flow , 2012 .
[9] Reinhard Wilhelm,et al. The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.
[10] Rolf Ernst,et al. Real-time performance analysis of multiprocessor systems with shared memory , 2010, TECS.
[11] Jürgen Becker,et al. Multiprocessor System-on-Chip - Hardware Design and Tool Integration , 2011, Multiprocessor System-on-Chip.
[12] Jakob Engblom,et al. The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.
[13] Raimund Kirner,et al. Towards Composable Timing for Real-Time Programs , 2009, 2009 Software Technologies for Future Dependable Distributed Systems.
[14] Jan Reineke,et al. Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Lothar Thiele,et al. Timing Analysis for TDMA Arbitration in Resource Sharing Systems , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.
[16] Edward A. Lee,et al. A PRET architecture supporting concurrent programs with composable timing properties , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.
[17] Robert I. Davis,et al. Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems , 2011, 2011 IEEE 32nd Real-Time Systems Symposium.
[18] Bernd Becker,et al. A Definition and Classification of Timing Anomalies , 2006, WCET.
[19] Lothar Thiele,et al. Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.
[20] David M. Brooks,et al. CPR: Composable performance regression for scalable multiprocessor models , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.