A Real-time Updatable FPGA-based Architecture for Fast Regular Expression Matching

Abstract In recent years, regular expression has been widely used in many network fields, but more and more applications require real-time update FSM and a space reduced DFA due to limited memory capacity. In this paper, we firstly propose a new architecture on FPGA supporting real-time update FSM, and design a special protocol for this update. Secondly, in order to support large-scale and complex semantic regular expression rule sets, we design an improved run-length encoding (iRLE) algorithm based on FPGA to reduce the DFA's storage space. The proposed algorithm gains a good compression ratio and requires only 2 clock cycles per a state transition. The experimental results also show that the new algorithm has both advantages of compressing ratio and speed, and the maximum throughput of the automaton can reach 10.7Gbps.