Function‐in‐layout: a demonstration with bio‐inspired hyperacuity chip

Below 100 nm a new scenario is emerging in VLSI design: floorplanning and function are inherently interrelated. Using mainly local connectivity, wire delay and crosstalk problems are eliminated. A new design methodology is proposed, called function-in-layout, that possesses: regular layout, mainly local connectivity, functional ‘parasitics’. A bio-inspired demonstration is presented, a hyperacuity chip, with 30 ps time difference detection using 0.35 mm complementary metal-oxide semiconductor (CMOS) technology. Copyright © 2006 John Wiley & Sons, Ltd.

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