The electron–hole bilayer tunnel FET

We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSavg ∼ 10 mV/dec over 7 decades of current) and Ion/Ioff > 10^8 at Vd = Vg = 0.5 V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the Ion (∼11 μA/μm at Vdd = 0.5 V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs.

[1]  A. M. Ionescu,et al.  Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation , 2012, IEEE Electron Device Letters.

[2]  K. Saraswat,et al.  Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope , 2008, 2008 IEEE International Electron Devices Meeting.

[3]  Adrian M. Ionescu,et al.  A new definition of threshold voltage in Tunnel FETs , 2008 .

[4]  M. Ancona,et al.  Macroscopic physics of the silicon inversion layer. , 1987, Physical review. B, Condensed matter.

[5]  V. Ramgopal Rao,et al.  A Binary Tunnel Field Effect Transistor with a Steep Sub-threshold Swing and Increased ON Current , 2010 .

[6]  A. Schenk.  A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon , 1992 .

[7]  Qin Zhang,et al.  Low-subthreshold-swing tunnel transistors , 2006, IEEE Electron Device Letters.

[8]  E. Kane.  Theory of Tunneling , 1961 .

[9]  Bo Zhang,et al.  Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator , 2009, IEEE Transactions on Electron Devices.

[10]  L. Nanver,et al.  Ultra-high aspect-ratio FinFET technology , 2010 .

[11]  G. Fiori,et al.  Ultralow-Voltage Bilayer Graphene Tunnel FET , 2009, IEEE Electron Device Letters.

[12]  J. Knoch,et al.  Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices , 2007 .

[13]  Geert Hellings,et al.  Electrical TCAD Simulations of a Germanium pMOSFET Technology , 2010, IEEE Transactions on Electron Devices.

[14]  K. Maex,et al.  Tunnel field-effect transistor without gate-drain overlap , 2007 .

[15]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.