Including the Effects of Process-Related Variability on Radiation Response in Advanced Foundry Process Design Kits

Space applications using advanced foundry processes require device models that accurately include the dependence of total-ionizing dose (TID) response on process variability and layout. An automated flow is described for TID-aware process design kit generation using new test chips, modeling, and simulation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.

[1]  R.,et al.  Challenges in hardening technologies using shallow-trench isolation , 1998 .

[2]  S.J. Lovett,et al.  Yield and matching implications for static RAM memory array sense-amplifier design , 2000, IEEE Journal of Solid-State Circuits.

[3]  O. Sidek,et al.  Layout dependence effect on high speed CMOS transistor leakage current , 2005, 2005 Asia-Pacific Conference on Applied Electromagnetics.

[4]  R.M.D.A. Velghe,et al.  CMOS device optimization for mixed-signal technologies , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5]  Xuemei Xi,et al.  A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[6]  peixiong zhao,et al.  Total Ionizing Dose Effects on Strained -Based nMOSFETs , 2008 .

[7]  Corbin Leigh Champion,et al.  Modeling of FETs with abnormal gate geometries for radiation hardening , 2004 .

[8]  G. Cervelli,et al.  Radiation-induced edge effects in deep submicron CMOS transistors , 2005, IEEE Transactions on Nuclear Science.

[9]  C.C. McAndrew,et al.  A comprehensive MOSFET mismatch model , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[10]  M. Tsukiji,et al.  Mechanical Stress Dependence of Radiation Effects in MOS Structures , 1986, IEEE Transactions on Nuclear Science.

[11]  T. Sanuki,et al.  Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique , 2008, 2008 Symposium on VLSI Technology.

[12]  J. Jacob Wikner,et al.  Influence of Circuit Imperfections on the Performance of DACs , 1999 .

[13]  P. Grignoux,et al.  Modeling of MOS transistors with nonrectangular-gate geometries , 1982, IEEE Transactions on Electron Devices.

[14]  S. Minehane,et al.  Characterization and modeling of MOSFET mismatch of a deep submicron technology , 2003, International Conference on Microelectronic Test Structures, 2003..

[15]  Marcel J. M. Pelgrom,et al.  Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[16]  T. Nishida,et al.  Total Ionizing Dose Effects on Strained ${\rm HfO}_{2}$-Based nMOSFETs , 2008, IEEE Transactions on Nuclear Science.

[17]  G.S. La Rue,et al.  Accurate SPICE models for CMOS analog radiation-hardness-by-design , 2005, IEEE Transactions on Nuclear Science.