Flexible and efficient reliability in memory systems

[1]  Wei Zhang,et al.  ICR: in-cache replication for enhancing data cache reliability , 2003, 2003 International Conference on Dependable Systems and Networks, 2003. Proceedings..

[2]  Daniel J. Sorin,et al.  Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache , 2006, 2006 International Conference on Computer Design.

[3]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[4]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[5]  Antonio Gonzalez,et al.  A data cache with multiple caching strategies tuned to different types of locality , 1995, International Conference on Supercomputing.

[6]  Abraham Silberschatz,et al.  Operating System Concepts , 1983 .

[7]  Peter Calingaert,et al.  Two-Dimensional Parity Checking , 1961, JACM.

[8]  E. Cannon,et al.  SRAM SER in 90, 130 and 180 nm bulk and SOI technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[9]  David Zhang,et al.  Secure program execution via dynamic information flow tracking , 2004, ASPLOS XI.

[10]  Stijn Eyerman,et al.  System-Level Performance Metrics for Multiprogram Workloads , 2008, IEEE Micro.

[11]  K. Osada,et al.  SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect , 2004, IEEE Journal of Solid-State Circuits.

[12]  Wei Wu,et al.  Improving cache lifetime reliability at ultra-low voltages , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[13]  Doe Hyun Yoon,et al.  Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[14]  James E. Smith,et al.  Implementing high availability memory with a duplication cache , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[15]  Balaram Sinharoy,et al.  POWER4 system microarchitecture , 2002, IBM J. Res. Dev..

[16]  Dwijendra K. Ray-Chaudhuri,et al.  Binary mixture flow with free energy lattice Boltzmann methods , 2022, arXiv.org.

[17]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[18]  Zhao Zhang,et al.  A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality , 2000, MICRO 33.

[19]  Timothy J. Dell,et al.  System RAS implications of DRAM soft errors , 2008, IBM J. Res. Dev..

[20]  Mahmut T. Kandemir,et al.  Soft error and energy consumption interactions: a data cache perspective , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[21]  Irina Adjudeanu,et al.  Codes correcteurs d'erreurs LDPC structurés , 2010 .

[22]  Arvind M. Patel,et al.  An adaptive error correction scheme for computer memory system , 1972, AFIPS '72 (Fall, part I).

[23]  Milo M. K. Martin,et al.  Hardbound: architectural support for spatial safety of the C programming language , 2008, ASPLOS.

[24]  C. L. Chen Symbol error correcting codes for memory applications , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[25]  Nhon Quach,et al.  High Availability and Reliability in the Itanium Processor , 2000, IEEE Micro.

[26]  R. Brett Tremaine,et al.  Durable memory RS/6000 system design , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[27]  Antonio María González Colás,et al.  Low Vccmin fault-tolerant cache with highly predictable performance , 2009, MICRO 2009.

[28]  Milo M. K. Martin,et al.  Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.

[29]  Frederick A. Ware,et al.  Improving Power and Data Efficiency with Threaded Memory Modules , 2006, 2006 International Conference on Computer Design.

[30]  Harish Patil,et al.  Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.

[31]  Babak Falsafi,et al.  Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[32]  Doe Hyun Yoon,et al.  Virtualized ECC: Flexible Reliability in Main Memory , 2011, IEEE Micro.

[33]  Pat Conway,et al.  The AMD Opteron Processor for Multiprocessor Servers , 2003, IEEE Micro.

[34]  Zhao Zhang,et al.  Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices , 2009, ISCA '09.

[35]  Yervant Zorian,et al.  Embedded memory reliability: the SER challenge , 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

[36]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[37]  P. Dodd,et al.  Radiation effects in SOI technologies , 2003 .

[38]  Sanjeev Kumar,et al.  Exploiting spatial locality in data caches using spatial footprints , 1998, ISCA.

[39]  Gabriel H. Loh,et al.  Zesto: A cycle-level simulator for highly detailed microarchitecture exploration , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[40]  Yale N. Patt,et al.  Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[41]  D. Strukov,et al.  The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[42]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[43]  Wei Zhang,et al.  Replication cache: a small fully associative cache to improve data cache reliability , 2005, IEEE Transactions on Computers.

[44]  R. Blahut Algebraic Codes for Data Transmission , 2002 .

[45]  Onur Mutlu,et al.  Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems , 2008, 2008 International Symposium on Computer Architecture.

[46]  H. Saito,et al.  Neutron-induced SEU in bulk and SOI SRAMS in terrestrial environment , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[47]  Aviral Shrivastava,et al.  Mitigating soft error failures for multimedia applications by selective data protection , 2006, CASES '06.

[48]  Mark D. Hill,et al.  Surpassing the TLB performance of superpages with less operating system support , 1994, ASPLOS VI.

[49]  Greg Hamerly,et al.  SimPoint 3.0: Faster and More Flexible Program Analysis , 2005 .

[50]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[51]  Krste Asanovic,et al.  Mondrian memory protection , 2002, ASPLOS X.

[52]  Doe Hyun Yoon,et al.  Flexible cache error protection using an ECC FIFO , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[53]  M. Ma,et al.  Impact of Error Correction Code and Dynamic Memory Reconfiguration on High-Reliability/Low-Cost Server Memory , 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

[54]  Anne Rogers,et al.  Software Caching and Computation Migration in Olden , 1996, J. Parallel Distributed Comput..

[55]  G. Tyson,et al.  Eager writeback-a technique for improving bandwidth utilization , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

[56]  Aamer Jaleel,et al.  DRAMsim: a memory system simulator , 2005, CARN.

[57]  Jeffrey D. Gilbert,et al.  Over one million TPCC with a 45nm 6-core Xeon® CPU , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[58]  Soontae Kim Area-Efficient Error Protection for Caches , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[59]  D. C. Bossen b-adjacent error correction , 1970 .

[60]  J. Maiz,et al.  Characterization of multi-bit soft error events in advanced SRAMs , 2003, IEEE International Electron Devices Meeting 2003.

[61]  Arun K. Somani,et al.  Area efficient architectures for information integrity in cache memories , 1999, ISCA.

[62]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[63]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[64]  Doe Hyun Yoon,et al.  Virtualized and flexible ECC for main memory , 2010, ASPLOS XV.

[65]  Zhao Zhang,et al.  Mini-rank: Adaptive DRAM architecture for improving memory power efficiency , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[66]  Steve Scott,et al.  The Cray BlackWidow: a highly scalable vector multiprocessor , 2007, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing (SC '07).

[67]  Rajesh K. Gupta,et al.  Adapting cache line size to application behavior , 1999, ICS '99.

[68]  Jeffrey B. Rothman,et al.  The pool of subsectors cache design , 1999, ICS '99.

[69]  Christoforos E. Kozyrakis,et al.  Future scaling of processor-memory interfaces , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[70]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[71]  Craig B. Zilles,et al.  Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory , 2008, 2008 International Symposium on Computer Architecture.

[72]  D. C. Bossen,et al.  Orthogonal latin square codes , 1970 .

[73]  Timothy J. Dell,et al.  A white paper on the benefits of chipkill-correct ecc for pc server main memory , 1997 .

[74]  A. Chandrakasan,et al.  A 256kb Sub-threshold SRAM in 65nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[75]  F. Jacquet,et al.  An alpha immune and ultra low neutron SER high density SRAM , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[76]  Maurice Steinman,et al.  ECC implementation in components without ECC , 2008 .

[77]  Alaa R. Alameldeen,et al.  Trading off Cache Capacity for Reliability to Enable Low Voltage Operation , 2008, 2008 International Symposium on Computer Architecture.

[78]  Wolf-Dietrich Weber,et al.  Power provisioning for a warehouse-sized computer , 2007, ISCA '07.

[79]  Doe Hyun Yoon,et al.  Memory mapped ECC: low-cost error protection for last level caches , 2009, ISCA '09.

[80]  Trevor N. Mudge,et al.  Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments , 2008, 2008 International Symposium on Computer Architecture.

[81]  Koushik Chakraborty,et al.  Mixed-mode multicore reliability , 2009, ASPLOS.

[82]  André Seznec,et al.  Decoupled sectored caches: conciliating low tag implementation cost , 1994, ISCA '94.

[83]  Jung Ho Ahn,et al.  Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs , 2009, IEEE Computer Architecture Letters.

[84]  Guru Venkataramani,et al.  FlexiTaint: A programmable accelerator for dynamic taint propagation , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[85]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[86]  Balaram Sinharoy,et al.  POWER7: IBM's next generation server processor , 2010, 2009 IEEE Hot Chips 21 Symposium (HCS).

[87]  E. A. Wolicki,et al.  Single Event Upset of Dynamic Rams by Neutrons and Protons , 1979, IEEE Transactions on Nuclear Science.

[88]  T. May,et al.  A New Physical Mechanism for Soft Errors in Dynamic Memories , 1978, 16th International Reliability Physics Symposium.

[89]  C. Morganti,et al.  The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[90]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[91]  Eduardo Pinheiro,et al.  DRAM errors in the wild: a large-scale field study , 2009, SIGMETRICS '09.

[92]  J. ContiC.,et al.  Structural aspects of the system/360 model 85 , 1968 .

[93]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[94]  Amir Roth,et al.  FIESTA: A Sample-Balanced Multi-Program Workload Methodology , 2009 .

[95]  R. Baumann,et al.  Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[96]  Kinam Kim,et al.  Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM , 2003, IEEE International Electron Devices Meeting 2003.

[97]  Tony M. Brewer,et al.  Instruction Set Innovations for the Convey HC-1 Computer , 2010, IEEE Micro.

[98]  Zhen Fang,et al.  The Impulse Memory Controller , 2001, IEEE Trans. Computers.

[99]  C.W. Slayman,et al.  Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations , 2005, IEEE Transactions on Device and Materials Reliability.

[100]  Babak Falsafi,et al.  Accurate and complexity-effective spatial pattern prediction , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).