Novel low area CMOS readout circuit for uncooled microbolometers with low noise

We propose a novel CMOS readout structure without sample and hold (SH) circuit for uncooled microbolometers. In this readout circuit, all the pixels in one row can be integrated simultaneously, and the readout integrated circuit (ROIC) area can be reduced by as much as 30%. Moreover, a single capacitor implementation of both capacitive transimpedance amplifier (CTIA) and correlated double sampling (CDS) is utilized to improve noise performance. An experimental 40x30 ROIC chip has been designed and fabricated with 0.5 μm CMOS technology. The test results show that the ROIC has good linearity with 260μV RMS total output noise voltage and 1800x650 μm2 total circuit area.