Evaluating High-Level Program Invariants Using Reconfigurable Hardware

There is an increasing concern about transient errors in deep sub-micron processor architectures. Software-only error detection approaches that exploit program invariants for silent error detection incur large execution overheads and are unreliable as state can be corrupted after invariant check points. In this paper we explore the use of configurable hardware structures for the continuous evaluation of high-level program invariants at the assembly-level. We evaluate the resource requirements and performance of the proposed hardware structures on a contemporary reconfigurable hardware device. The results, for a small set of kernels codes, reveal that these hardware structures require a very small number of resources and are fairly insensitive to the complexity of the invariants thus making the proposed hardware approach an attractive alternative to software-only invariant checking by integrating them in traditional processor architectures.