A cache consistency protocol for multiprocessors with multistage networks

A hardware based cache consistency protocol for multiprocessors with multistage networks is proposed. Consistency traffic is restricted to the set of caches which have a copy of a shared block. State information is distributed to the caches and the memory modules need not be consulted for consistency actions. The protocol provides two operating modes: distributed write and global read. Distribution of writes calls for efficient multicast methods. Communication cost for multicasting is analyzed and a novel scheme is proposed. Finally, communication cost for the protocol is compared to other protocols. The two-mode approach limits the upperbound for the communication cost to a value considerably lower than that for other protocols.

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