Reconfigurable back enhanced (BE) SOI MOSFET used to build a logic inverter

This paper reports the characteristics and the operation of the new BE SOI MOSFET used to build a logic inverter for the first time. The main characteristics of this device is its simplicity of fabrication and the reconfigurable behavior, i.e, it can act as a n-type transistor or as a p-type transistor depending on the back gate bias. Furthermore, an inverter circuit was built and the static response was measured. The BE SOI inverter showed a characteristic CMOS inverter curve. Finally, the threshold voltage variation with the silicon and gate oxide thickness is explored in order to find the best inverter circuit design.

[1]  Maud Vinet,et al.  (Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities , 2016 .

[2]  Stefan Slesazeck,et al.  Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors , 2014, IEEE Electron Device Letters.

[3]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[4]  Hiroshi Iwai Future of nano CMOS technology , 2014, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits.

[5]  M. Vinet,et al.  Reconfigurable field effect transistor for advanced CMOS: A comparison with FDSOI devices , 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[6]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[7]  J. Martino,et al.  Back Enhanced (BE) SOI pMOSFET , 2015, 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro).

[8]  Udo Schwalke,et al.  Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS , 2016, 2016 13th International Multi-Conference on Systems, Signals & Devices (SSD).

[9]  Thomas Mikolajick,et al.  Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform , 2016 .

[10]  U. Schwalke,et al.  Dopant-Free CMOS on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications , 2013 .

[11]  Thomas Mikolajick,et al.  Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors , 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[12]  L. Le Pailleur Fully-depleted-silicon-on-insulator from R&D concept to industrial reality , 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[13]  O. Rozeau,et al.  Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit , 2011, IEEE Transactions on Electron Devices.

[14]  Liesbeth Witters,et al.  Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession , 2010 .

[15]  Udo Schwalke,et al.  Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs , 2013, Microelectron. J..

[16]  J. Martino,et al.  Back Enhanced (BE) SOI MOSFET under non-conventional bias conditions , 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[17]  R.V.H. Booth,et al.  Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's , 1987 .