A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model

Electromigration (EM) has been considered to be a severe reliability issue in power grid networks of large integrated circuits (IC). The via array possesses special EM characteristics that have been observed to be distinct from a single via. In this study, a compact analytical model for the fast estimation of EM for via array was proposed by calculating the current distribution in the via arrays. The proposed model was then analyzed in a multi-layer power grid, which, for the first time, considered the impacts of the current propagation that exists in the vertical via array connected within the multi-level interconnection to improve the accuracy of the analytical model further. According to the model, a novel methodology for full- chip EM checking for multi-layered power grids was proposed. This method factored in the routing structure of the multi-layer power grid network, ensuring the EM assessment analysis's efficiency for large-scale power grid networks without sacrificing accuracy.