A 2.3e- Read Noise 1.3Mpixel CMOS Image Sensor with Per-Column Amplifier

Low-noise, low-power, area-efficient CMOS imager readout architecture is studied through four 1.3Mpixel test chips using the same pixel array and silicon area. By employing per-column amplifier in front of column sample-and-hold circuitry and utilizing the extended correlateddouble-sampling[1,2] principle, a low 2.3eread noise is achieved, as compared to 4.2ewith conventional serial analog multi-stage readout chain architecture. The gain stages and 10-bit pipelined analog-to-digital converter (ADC) featured the shared-amplifier with short-reset scheme [3] delivered a maximum of 64x analog gain with differential nonlinearity (DNL) +0.3/-0.6 least significant bit (LSB) and integral nonlinearity (INL) +1.2/-0.75 LSB with 50% lower power consumption.