Look-up table leakage reduction for FPGAs

We propose new programmable FPGA look-up tables (LUTs) that can operate in two different modes: high-performance or low-power. Selection between the two modes is realized by an extra SRAM cell that can be shared by a number of LUTs. In high-performance mode, the LUTs provide similar power and performance to a conventional LUT. In low-power mode, one LUT reduces leakage by 53%, while another reduces leakage by 53% and 80% when outputting a logic-0 and logic-1 respectively, which can lead to an average leakage reduction of up to 76%. In low-power mode, delay is increased by 5% to 20% compared to a conventional LUT. The technique scales well and reduces further leakage for new FPGA architectures that use larger size LUTs.

[1]  Vaughn Betz,et al.  The Stratix II logic and routing architecture , 2005, FPGA '05.

[2]  Jason Cong,et al.  Architecture evaluation for power-efficient FPGAs , 2003, FPGA '03.

[3]  David Blaauw,et al.  Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[4]  Arifur Rahman,et al.  Evaluation of low-leakage design techniques for field programmable gate arrays , 2004, FPGA '04.

[5]  Zeljko Zilic,et al.  Dynamic clock management for low power applications in FPGAs , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[6]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[7]  Jan M. Rabaey,et al.  Low-Energy FPGAs - Architecture and Design , 2001 .

[8]  Bo-Cheng Lai,et al.  Leakage power analysis of a 90nm FPGA , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[9]  Kouichi Kumagai,et al.  A novel powering-down scheme for low Vt CMOS circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[10]  Jason Helge Anderson,et al.  A novel low-power FPGA routing switch , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[11]  SinghAmit,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002 .

[12]  Stefan Kubicek,et al.  Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .

[13]  Tim Tuan,et al.  Active leakage power optimization for FPGAs , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  George Varghese,et al.  The design of a low energy FPGA , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).