Parallel and Runtime Reconfigurable Implementation of the Idea Algorithm

Cryptographic algorithms are a fundamental tool nowadays, and information networks continue to grow exponentially every year. Moreover, these algorithms need to be very fast due to the new standards. In order to achieve this characteristic, a good choice is to use FPGAs, which mix the advantages of software flexibility and hardware performance. In this work, we present a super-pipelined and parallel implementation of the IDEA cryptographic algorithm by using partial and dynamic reconfiguration. Our implementation reaches a performance of 26.028 Gb/s, and therefore, it obtains better results than those found in the literature.