A High-Performance Energy-Efficient 75.17 dB Two-Stage Operational Amplifier

This paper discusses the design and analysis of two-stage CMOS operational amplifier. This design is operated at the supply of 1.5 V in 90 nm CMOS technology. In this design, 75.17 dB open-loop gain is achieved and having 7.73 MHz unity gain bandwidth and 148.8 m degree phase margin. This circuit has 10 pF capacitive load with 0.14 nW average power dissipation and slew rate is 0.25 V/μs. This proposed circuit is designed and simulated in cadence UMC 90 nm technology.

[1]  S.S. Jamuar,et al.  Design of low voltage operational amplifier , 2004, 2004 IEEE International Conference on Semiconductor Electronics.

[2]  Ketan J. Raut,et al.  A 180 nm low power CMOS operational amplifier , 2014, 2014 Innovative Applications of Computational Intelligence on Power, Energy and Controls with their impact on Humanity (CIPECH).

[3]  M. Bala,et al.  Design of Low Voltage Low Power Operational Amplifier , 2012, 2012 Second International Conference on Advanced Computing & Communication Technologies.

[4]  Kenneth W. Martin,et al.  Analog integrated circuit design. 2nd ed. , 2012 .

[5]  Manoj Duhan,et al.  Design of Two Stage Op-Amp , 2013 .