Several Problems in Design for Testability of SoC

This paper introduces several important problems in design for testability of SoC,including how to control clocks,resets,bidirectional ports,internal tristate buses and how to deal with combinational loops,latches,mixing edge triggered flip flops,shadow logic in scan design for general functional modules,as well as how to select the architecture and algorithm in builtin selftest design for embedded memory.We also give the specific methods in practical design for testability of a SoC based on ARM processor.