Slice Analysis Based Bayesian Power Model for Sequential Circuits

Bayesian modeling method and slice anal- ysis techniques show good efiect in cycle-accurate power analysis of combinational circuit. In this paper, we use vir- tual signal logical depth assignment to resolve the problem that signal loop can not be sliced in sequential circuits. With this method, we build cycle-accurate power model based on Bayesian inference and slice analysis techniques. The experiments on ISCAS89 benchmark show that the power-per-cycle estimation error is 6.7%. By analyzing the relation between error trend under difierent slices and cir- cuit's size, we also build a thumb rule about how to choose best slice number: when the accumulative gate number is about 73% of total gate number, the model error with slice-based parameters usually arrives minimum value. In probability based method, inner node switching proba- bility is computed based on port signal probability. The com- putation is conducted through symbolic simulation and the switching probability is calculated by level sequence. Ref.(9) proposed a modeling method based on signal switching proba- bility, but the calculation cost is huge to large circuit module, for the STG (State transition graph) and complicated expan- sion computation for circuit state are needed. In Ref.(10), state probabilities can be computed using the Chapman- Kolmogorov equations, and present state line probabilities are computed by solving a system of nonlinear equations. But this method supposes that there is no temporal correlation among signals, and calculation cost increases rapidly when module becomes larger, since each register state is needed in compu- tation. Ref.(11) proposed building power model by using hierarchi- cal colored hardware Petri net, Refs.(12, 13) used dynamical Bayesian network to calculate each inner node switching prob- ability of sequential circuit. But those methods all have the requirement of each node's information, which results in huge calculation and bad scalability. Refs.(14, 15) discussed the sig- nal correlation in modeling and modeling method based on gate type, but those methods could only be used in combina- tion circuits. To resolve the problem of cycle accurate power model- ing for sequential circuits, we propose that use slice analysis to extract characteristic information, and build power model through Bayesian inference. We use virtual signal logical depth assignment to resolve the problem of signal loop can not be sliced in sequential circuits. The experiment shows the power- per-cycle estimation error is 6.7% and estimation speed-up is 572. We also discuss the relationship between best slice num- ber and circuit characteristic, summarizing a thumb rule to help the best slice number selecting and validating this thumb rule by the experiment on data-path module in PKUnity863 SoC.