论文信息 - Hardware implementation of an expandable on-chip learning neural network with 8-neuron and 64-synapse

Hardware implementation of an expandable on-chip learning neural network with 8-neuron and 64-synapse

An expandable on-chip learning neural network chip with 8-neuron and 64-synapse is designed and fabricated with a standard 0.6 /spl mu/m CMOS technology. Large-scale neural network with arbitrary layers can be constructed by connecting unit chips. A novel neuron circuit with programmable parameters is proposed. It generates riot only the sigmoid function but also its derivative. The neuron has a push-pull output stage to gain strong driving ability in both charge and discharge processes, which is very important in heavy load situations. An improved Gilbert multiplier is also proposed. It has one end current output and precise zero point. The learning system itself can be used as a refresh tool to keep the weight value right. Experiment results show that it has good performance.

[1] 石秉学,et al. Circuit Design of On—Chip BP Learning Neural Network with … , 2000 .

[2] Daniele D. Caviglia,et al. An experimental analog VLSI neural network with on-chip back-propagation learning , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[3] Tor Sverre Lande,et al. An analog feed-forward neural network with on-chip learning , 1996 .

[4] Anne J. Annema. Hardware realisation of a neuron transfer function and its derivative , 1994 .

[5] Gert Cauwenberghs,et al. An analog VLSI recurrent neural network learning a continuous-time trajectory , 1996, IEEE Trans. Neural Networks.

[6] Bingxue Shi,et al. Circuit design of an adjustable neuron activation function and its derivative , 2000 .

[7] Howard C. Card,et al. Tolerance to analog hardware of on-chip learning in backpropagation networks , 1995, IEEE Trans. Neural Networks.

[8] G. Bogason. Generation of a neuron transfer function and its derivatives , 1993 .