A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 μm CMOS process occupies 0.35 mm 2 active area. From a 1.8 V supply, it consumes 59 mW and 984 μW during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

[1]  Changsik Yoo,et al.  Digitally controlled phase locked loop with tracking analog-to-digital converter , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[2]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[3]  Thomas Olsson,et al.  A digitally controlled PLL for digital SOCs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[5]  Hyung-Kyu Lim,et al.  A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL , 1997 .

[6]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[8]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.