Efficient controller synthesis for a fragment of MTL 0 , &infin
暂无分享,去创建一个
Kim Guldstrand Larsen | Guangyuan Li | Peter E. Bulychev | Alexandre David | Peter Bulychev | K. Larsen | Guangyuan Li | Alexandre David
[1] Kim G. Larsen,et al. Efficient On-the-Fly Algorithms for the Analysis of Timed Games , 2005, CONCUR.
[2] Kim G. Larsen,et al. Monitor-Based Statistical Model Checking for Weighted Metric Temporal Logic , 2012, LPAR.
[3] P. Ramadge,et al. Supervisory control of a class of discrete event processes , 1987 .
[4] J. R. Büchi,et al. Solving sequential conditions by finite-state strategies , 1969 .
[5] Pierre Wolper,et al. Synthesis of Communicating Processes from Temporal Logic Specifications , 1981, Logic of Programs.
[6] Rajeev Alur,et al. Formal verification of hybrid systems , 2011, 2011 Proceedings of the Ninth ACM International Conference on Embedded Software (EMSOFT).
[7] Orna Kupferman,et al. Safraless Compositional Synthesis , 2006, CAV.
[8] Amir Pnueli,et al. Specify, Compile, Run: Hardware from PSL , 2007, COCV@ETAPS.
[9] Joël Ouaknine,et al. On the decidability of metric temporal logic , 2005, 20th Annual IEEE Symposium on Logic in Computer Science (LICS' 05).
[10] Vojtech Rehák,et al. LTL to Büchi Automata Translation: Fast and More Deterministic , 2012, TACAS.
[11] Edmund M. Clarke,et al. Using Branching Time Temporal Logic to Synthesize Synchronization Skeletons , 1982, Sci. Comput. Program..
[12] Amir Pnueli,et al. Synthesis of Reactive(1) Designs , 2006, VMCAI.
[13] Amir Pnueli,et al. On the synthesis of a reactive module , 1989, POPL '89.
[14] Jean-François Raskin,et al. Safraless Procedures for Timed Specifications , 2010, FORMATS.
[15] Howard Bowman,et al. Efficient Detection of Zeno Runs in Timed Automata , 2007, FORMATS.
[16] Véronique Bruyère,et al. Acacia+, a Tool for LTL Synthesis , 2012, CAV.
[17] Jean-François Raskin,et al. Realizability of Real-Time Logics , 2009, FORMATS.
[18] Kim G. Larsen,et al. A Tutorial on Uppaal , 2004, SFM.
[19] Jean-François Raskin,et al. Exploiting structure in LTL synthesis , 2013, International Journal on Software Tools for Technology Transfer.
[20] Kim G. Larsen,et al. UPPAAL-Tiga: Time for Playing Games! , 2007, CAV.
[21] Kim G. Larsen,et al. Tools for Model-Checking Timed Systems , 2013, Communicating Embedded Systems.
[22] Dejan Nickovic,et al. On Synthesizing Controllers from Bounded-Response Properties , 2007, CAV.
[23] Jean-François Raskin,et al. An Antichain Algorithm for LTL Realizability , 2009, CAV.
[24] Patricia Bouyer,et al. Controller Synthesis for MTL Specifications , 2006, CONCUR.
[25] D. Kozen. Results on the Propositional µ-Calculus , 1982 .
[26] Rajeev Alur,et al. A Theory of Timed Automata , 1994, Theor. Comput. Sci..
[27] Dejan Nickovic,et al. Real Time Temporal Logic: Past, Present, Future , 2005, FORMATS.
[28] Thomas A. Henzinger,et al. The benefits of relaxing punctuality , 1991, JACM.
[29] Joseph Sifakis,et al. On the Synthesis of Discrete Controllers for Timed Systems (An Extended Abstract) , 1995, STACS.
[30] Rüdiger Ehlers,et al. Symbolic bounded synthesis , 2010, Formal Methods Syst. Des..