Analog Power-Down Synthesis

Modern system-on-chip designs implement sophisticated power management features to achieve better energy efficiency. This includes power-down modes for analog circuit blocks. Typically, they are implemented by additional power-down circuitry which shuts down all bias currents. During the design of power-down circuitry, it must be ensured that the circuit still meets all specifications in normal operation. Furthermore, floating nodes and asymmetric stress need to be avoided in order to reduce device degradation over time. Therefore, the manual design of power-down circuitry can become a challenging and time consuming task requiring alternating implementation and verification phases. In this paper, a power-down synthesis methodology is presented which constructs fault-free power-down circuitry by systematically applying typical shutoff patterns. Furthermore, the synthesized power-down circuitry is visualized in the circuit schematic to support the designer in capturing the structure of the inserted power-down circuitry. Finally, the sizing of power-down transistors is determined automatically. Experimental results for three amplifier circuits, a voltage controlled ring oscillator and a low voltage differential signaling driver demonstrate the efficiency and efficacy of the presented methods.