Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction

Today’s Real-Time Systems’ (RTSs) increasing speed and complexity make debugging of timing related faults one of the most challenging engineering tasks. Debugging starts with capturing the fault symptoms, which requires continuous cycle-accurate execution traces. However, due to limitations of on-chip buffers’ area and output ports’ throughput, these cannot be obtained easily.

[1]  Markus Wedler,et al.  Formal hardware/software co-verification by interval property checking with abstraction , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  Somesh Jha,et al.  Dynamic Behavior Matching: A Complexity Analysis and New Approximation Algorithms , 2011, CADE.

[3]  Sanjit A. Seshia,et al.  Post-silicon validation opportunities, challenges and recent advances , 2010, Design Automation Conference.

[4]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  Fadi J. Kurdahi,et al.  NUVA: Architectural support for runtime verification of parametric specifications over multicores , 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[6]  Alan J. Hu,et al.  BackSpace: Formal Analysis for Post-Silicon Debug , 2008, 2008 Formal Methods in Computer-Aided Design.

[7]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[8]  Azadeh Davoodi,et al.  Trace signal selection to enhance timing and logic visibility in post-silicon validation , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Kees Goossens,et al.  Debugging Systems-on-Chip , 2014 .

[10]  Nur A. Touba,et al.  Enhancing Silicon Debug via Periodic Monitoring , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[11]  Armin Biere,et al.  Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays , 2009, TACAS.

[12]  Thomas Schuster,et al.  SoCRocket - A virtual platform for the European Space Agency's SoC development , 2014, 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[13]  Kees Goossens,et al.  Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques , 2014 .

[14]  Reinhold Heckmann,et al.  Computing the Worst Case Execution Time of an Avionics Program by Abstract Interpretation , 2007 .

[15]  Markus Wedler,et al.  A New Formal Verification Approach for Hardware-dependent Embedded System Software , 2013, IPSJ Trans. Syst. LSI Des. Methodol..

[16]  Matthias Függer,et al.  Runtime verification of embedded real-time systems , 2014, Formal Methods Syst. Des..

[17]  Subhasish Mitra,et al.  IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors , 2008, 2008 45th ACM/IEEE Design Automation Conference.