AFRA: A low cost high performance reliable routing for 3D mesh NoCs

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively. Furthermore, AFRA, as will be proved, is deadlock-free when all vertical faulty links have the same direction. This enables the routing to save virtual channels for performance rather than scarifying them for deadlock avoidance. Finally, AFRA provides robustness, which means supporting connection for all possible pairs of communicating nodes in high fault rates. AFRA is evaluated, though cycle accurate network simulation, and is compared with planar adaptive routing. Results reveal that AFRA significantly outperforms planar adaptive routing in both synthetic and real traffic patterns. In addition, the robustness of AFRA is calculated analytically.

[1]  John Kim,et al.  Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[2]  Antonio Robles,et al.  A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes , 2004, NPC.

[3]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[4]  Lorena Anghel,et al.  RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[5]  TingTing Hwang,et al.  TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[6]  Andrew A. Chien,et al.  Planar-adaptive routing: low-cost adaptive networks for multiprocessors , 1992, ISCA '92.

[7]  Luca Benini,et al.  Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Hsien-Hsin S. Lee,et al.  Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory , 2010, IEEE Custom Integrated Circuits Conference 2010.

[9]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[10]  José Duato,et al.  Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs , 2009 .

[11]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[12]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[13]  Federico Silla,et al.  Fault-Tolerant Vertical Link Design for Effective 3D Stacking , 2011, IEEE Computer Architecture Letters.

[14]  Hannu Tenhunen,et al.  Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[15]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[16]  Arvind Kumar,et al.  Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..

[17]  P. Arunasalam,et al.  Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[18]  Jie Wu,et al.  A simple fault-tolerant adaptive and minimal routing approach in 3-D meshes , 2008, Journal of Computer Science and Technology.

[19]  Jie Wu,et al.  Fault-tolerant routing in meshes/tori using planarly constructed fault blocks , 2005, 2005 International Conference on Parallel Processing (ICPP'05).