Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an application-specific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8×8 array multiplier, bitwise XOR operation and a 3 × 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared.

[1]  Zainalabedin Navabi,et al.  VHDL: Analysis and Modeling of Digital Systems , 1992 .

[2]  Elena Dubrova,et al.  Fault-Tolerant Design , 2013 .

[3]  Yan Han,et al.  An SET hardened dual-modular majority voter circuit for TMR system , 2014, IEICE Electron. Express.

[4]  Xiaoxuan She,et al.  Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation , 2009, IEEE Transactions on Nuclear Science.

[5]  J. Teifel,et al.  Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation , 2008, IEEE Transactions on Nuclear Science.

[6]  V. Elamaran,et al.  Low Energy, Low Power Adder Logic Cells: A CMOS VLSI Implementation , 2014 .

[7]  Zvonko G. Vranesic,et al.  Fundamentals of Digital Logic with VHDL Design , 2008 .

[8]  Zainalabedin Navabi,et al.  Embedded Core Design with FPGAs , 2006 .

[9]  Farouk Smith.  A new methodology for single event transient suppression in flash FPGAs , 2013, Microprocess. Microsystems.

[10]  V. Elamaran,et al.  CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach , 2015 .

[11]  J. A. Maestro,et al.  A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs , 2009, IEEE Transactions on Nuclear Science.

[12]  V. Elamaran,et al.  FPGA Implementation of Self-Testing Logic Gates, Adders and Multipliers , 2015 .

[13]  P. K. Lala.  Self-Checking and Fault-Tolerant Digital Design , 1995 .

[14]  P. Balasubramanian,et al.  A distributed minority and majority voting based redundancy scheme , 2015, Microelectron. Reliab..

[15]  L. W. Massengill,et al.  Single Event Transients in Digital CMOS—A Review , 2013, IEEE Transactions on Nuclear Science.

[16]  Gustavo A. Ruiz,et al.  An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit , 2004, Microelectron. J..

[17]  V. Elamaran,et al.  Low Power Digital Barrel Shifter Datapath Circuits Using Microwind Layout Editor with High Reliability , 2015 .

[18]  Diana Marculescu,et al.  Circuit Reliability Analysis Using Symbolic Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Rajendra M. Patrikar,et al.  Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits , 2009, Microelectron. Reliab..

[20]  Lirida A. B. Naviner,et al.  Progressive module redundancy for fault-tolerant designs in nanoelectronics , 2011, Microelectron. Reliab..

[21]  John P. Uyemura.  Introduction to VLSI Circuits and Systems , 2001 .