The Benefit of Concurrency in Model Checking
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[1] Alan Mishchenko,et al. A single-instance incremental SAT formulation of proof- and counterexample-based abstraction , 2010, Formal Methods in Computer Aided Design.
[2] Robert K. Brayton,et al. ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.
[3] Aaron R. Bradley. k-Step Relative Inductive Generalization , 2010, ArXiv.
[4] Jason Baumgartner,et al. Enhanced verification by temporal decomposition , 2009, 2009 Formal Methods in Computer-Aided Design.
[5] Lubos Brim,et al. CUDA Accelerated LTL Model Checking , 2009, 2009 15th International Conference on Parallel and Distributed Systems.
[6] Gianpiero Cabodi,et al. Speeding up model checking by exploiting explicit and hidden verification constraints , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[7] Robert K. Brayton,et al. Speculative reduction-based scalable redundancy identification , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[8] Ziv Nevo,et al. User-Friendly Model Checking: Automatically Configuring Algorithms with RuleBase/PE , 2009, Haifa Verification Conference.
[9] Michael L. Case,et al. Scalable and scalably-verifiable sequential synthesis , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[10] Zohar Manna,et al. Checking Safety by Inductive Generalization of Counterexamples to Induction , 2007, Formal Methods in Computer Aided Design (FMCAD'07).
[11] Robert K. Brayton,et al. Fast Minimum-Register Retiming via Binary Maximum-Flow , 2007, Formal Methods in Computer Aided Design (FMCAD'07).
[12] Jason Baumgartner,et al. Scalable Sequential Equivalence Checking across Arbitrary Design Transformations , 2006, 2006 International Conference on Computer Design.
[13] Robert K. Brayton,et al. DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[14] Jason Baumgartner,et al. Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies , 2005, CHARME.
[15] Jason Baumgartner,et al. Exploiting suspected redundancy without proving it , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[16] Per Bjesse,et al. Automatic generalized phase abstraction for formal verification , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[17] Jason Baumgartner,et al. Scalable Automated Verification via Expert-System Guided Transformations , 2004, FMCAD.
[18] Malay K. Ganai,et al. Iterative abstraction using SAT-based BMC with proof analysis , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[19] Kenneth L. McMillan,et al. Interpolation and SAT-Based Model Checking , 2003, CAV.
[20] Kenneth L. McMillan,et al. Automatic Abstraction without Counterexamples , 2003, TACAS.
[21] Armin Biere,et al. Bounded Model Checking Using Satisfiability Solving , 2001, Formal Methods Syst. Des..
[22] Jiang Long,et al. Smart simulation using collaborative formal and simulation engines , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[23] Edmund M. Clarke,et al. Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Limor Fix,et al. Fifteen Years of Formal Property Verification in Intel , 2008, 25 Years of Model Checking.