An SEM based system for a complete characterization of latch-up in CMOS integrated circuits

An electron beam testing system was established for a complete and detailed analysis of latch-up in CMOS integrated circuits. Problems which can be studied include: (a) identification of latch-up current paths in steady state condition; (b) measurement of the local latch-up sensitivity of the various parts of the circuit; (c) observation of the time evolution of latch-up from the firing event to the final condition.

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