PERFLEX: a performance driven module generator

A performance-driven approach to module generation, called PERFLEX, for static combinational CMOS logic circuits is described. The flexible layout style supports implementation of fast and reliable circuits. Improvement in circuit speed is achieved through minimization of diffusion and interconnection capacitance, transistor sizing, and transistor reordering. By integrating transistor sizing and reordering steps in the layout process, fine-grain optimization is achieved. Experimental results are presented.<<ETX>>

[1]  Malgorzata Marek-Sadowska,et al.  Pin assignment for improved performance in standard cell design , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[3]  庄司 正一.  CMOS digital circuit technology , 1988 .

[4]  Vishwani D. Agrawal,et al.  Chip Layout Optimization Using Critical Path Weighting , 1984, 21st Design Automation Conference Proceedings.

[5]  Sung-Mo Kang.  Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout , 1987, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  David Marple.  Transistor Size Optimization in the Tailor Layout System , 1989, 26th ACM/IEEE Design Automation Conference.

[7]  Sung-Mo Kang,et al.  A new circuit optimization technique for high performance CMOS circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  A.D. Lopez,et al.  A Dense Gate Matrix Layout Method for MOS VLSI , 1980, IEEE Journal of Solid-State Circuits.

[9]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[10]  Dwight D. Hill,et al.  Experiments using automatic physical design techniques for optimizing circuit performance , 1990, IEEE International Symposium on Circuits and Systems.

[11]  Hugo De Man,et al.  Timing verification using statically sensitizable paths , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Douglass J. Wilde,et al.  Foundations of Optimization. , 1967 .

[14]  Robert K. Brayton,et al.  Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network , 1989, 26th ACM/IEEE Design Automation Conference.

[15]  Ernest S. Kuh,et al.  An Algorithm for Performance-Driven Placement of Cell-Based ICs , 1991 .

[16]  Soohong Kim.  CMOS VLSI layout synthesis for circuit performance , 1992 .

[17]  Alberto Sangiovanni-Vincentelli,et al.  Optimization-based transistor sizing , 1988 .

[18]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[19]  Malgorzata Marek-Sadowska,et al.  Timing driven placement , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.