Communication on HC16 - A Study of Methods and Performance in a Hypercubic Network Based on Dual Port RAM

This paper describes how Dual Fort Memory chips are used to make a highly efficient communication network for a hypercube computer, HC16-186. A single chip is used as a simple and inexpensive way to interconnect pair of processors. The bandwidth and message latency for the system compares favorably with much more complex hardware. The peak bandwidth has been measured to 1.8 MBytes/s, which is 3 times better than Intel iPSC/2 with comparable message lengths. A 135 j~s message latency is comparable with Mark-III, and again more than 3 times better than iPSC12. It should also be noted that iPSC/2 and Mark-III are based on more powerful hardware and are therefore expected to perform significantly better than the machine described here.