Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency fT, maximum oscillation frequency fmax, transconductance frequency product, higher order transconductance coefficients (gm1, gm3), VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HDGAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

[1]  W. Choi,et al.  Hetero-Gate-Dielectric Tunneling Field-Effect Transistors , 2010, IEEE Transactions on Electron Devices.

[2]  A. Mallik,et al.  Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications , 2012, IEEE Transactions on Electron Devices.

[3]  Jin He,et al.  An Analytical Charge Model for Double-Gate Tunnel FETs , 2012, IEEE Transactions on Electron Devices.

[4]  R. S. Gupta,et al.  Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design , 2008 .

[5]  K. Boucart,et al.  Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric , 2007 .

[6]  J.C.S. Woo,et al.  The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor , 2008, IEEE Transactions on Electron Devices.

[7]  Ching-Te Chuang,et al.  Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET , 2013, IEEE Transactions on Electron Devices.

[8]  Ian A. Young,et al.  Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[9]  Min-Chul Sun,et al.  Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology , 2011 .

[10]  N. Singh,et al.  New degradation mechanisms and reliability performance in tunneling field effect transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[11]  A. Mallik,et al.  Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor , 2011, IEEE Transactions on Electron Devices.

[12]  K. Boucart,et al.  Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.

[13]  Richard S. Muller,et al.  Analysis of MOSFET degradation due to hot-electron stress in terms of interface-state and fixed-charge generation , 1988 .

[14]  N. Singh,et al.  Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires , 2009, IEEE Electron Device Letters.

[15]  Doris Schmitt-Landsiedel,et al.  Complementary tunneling transistor for low power application , 2004 .

[16]  K. Maex,et al.  Tunnel field-effect transistor without gate-drain overlap , 2007 .

[17]  Te-Kuang Chiang,et al.  A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges , 2011, IEEE Transactions on Electron Devices.

[18]  S. K. Mohapatra,et al.  Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET , 2014, Microelectron. J..

[19]  D. Esseni,et al.  Impact of interface traps on the IV curves of InAs Tunnel-FETs and MOSFETs: A full quantum study , 2012, 2012 International Electron Devices Meeting.

[20]  Runsheng Wang,et al.  A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET , 2014, IEEE Transactions on Electron Devices.

[21]  Ru Huang,et al.  Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability , 2013, IEEE Transactions on Electron Devices.

[22]  Rishu Chaujar,et al.  Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor , 2015 .

[23]  Sung Hwan Kim,et al.  Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs , 2011, IEEE Transactions on Electron Devices.

[24]  M. J. Kumar,et al.  Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor , 2011, IEEE Transactions on Electron Devices.