H.264/AVC Intra Predictor on a Coarse-Grained Reconfigurable Multi-Media System

Coarse-Grained Reconfigurable Architectures (CGRA) have proved to be the potential candidates to meet the high performance, low power and flexibility required by embedded systems. In this paper, we implemented a High Profile Intra Predictor for H.264/AVC decoder on a novel coarse-grained reconfigurable processor- Remus (Reconfigurable Multi-media System). We proposed the pipeline and parallel scheduling process for intra prediction algorithm and the simulation results show that 548 clock cycles are consumed for the worst case of intra macro blocks.

[1]  Liang-Gee Chen,et al.  Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[2]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[3]  Wenjie Wang,et al.  A reconfigurable multi-processor SoC for media applications , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[4]  Leibo Liu,et al.  A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System , 2010, IEICE Trans. Inf. Syst..

[5]  Bjorn De Sutter,et al.  Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder , 2008, J. Signal Process. Syst..

[6]  Thomas Wiegand,et al.  Draft ITU-T recommendation and final draft international standard of joint video specification , 2003 .