论文信息 - On structured gate forest VLSI design

On structured gate forest VLSI design

Abstract The opportunities for structured VLSI design on a Sea-of-Gates template are discussed. From a critique on the use of standard cells, the Gate Forest approach for testable module compilation is introduced. With suitable tooling architectured in an open CAD environment, this allows for almost Full Custom layout efficiency.

Thomas Schwederski | Bernd Hoefflinger | Jens Dr Leenstra | Gerhard Roos | Lambert Spaanenburg

[1] Cees J. Koomen. The entropy of design: A study on the meaning of creativity , 1985, IEEE Transactions on Systems, Man, and Cybernetics.

[2] Michael L. Bushnell,et al. Automated design tool execution in the Ulysses design environment , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3] Nicolaas Mars,et al. A knowledge-based approach to VLSI-design in an open CAD-environment , 1989 .

[4] J. Kernhof,et al. Characteristics and requirements of semi-custom design tools , 1989 .

[5] J. Kernhof,et al. New directions in semicustom arrays , 1988 .

[6] P. Six,et al. Cathedral-II: A Silicon Compiler for Digital Signal Processing , 1986, IEEE Design & Test of Computers.

[7] C. F. Fey,et al. Studies in LSI technology economics. III. Design schedules for application-specific integrated circuits , 1987 .

[8] Fadi J. Kurdahi,et al. Techniques for area estimation of VLSI layouts , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9] B. Hoefflinger,et al. The CMOS gate forest: an efficient and flexible high-performance ASIC design environment , 1988, IEEE J. Solid State Circuits.

[10] L. Spaanenburg,et al. Using hierarchy in macro cell test assembly , 1989, [1989] Proceedings of the 1st European Test Conference.