TSV Interface for DRAM

This topic is Thru Silicon Via interface for DRAM. This part will explain why TSV is necessary in DRAM, the advantages of DRAM with TSV, the TSV DRAM types and the issues and solutions for the TSV DRAM.

[1]  Young-Hyun Jun,et al.  A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.

[2]  D. Malta,et al.  Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[3]  Chulwoo Kim,et al.  An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5]  Chulwoo Kim,et al.  A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface , 2012, 2012 IEEE International Solid-State Circuits Conference.

[6]  TingTing Hwang,et al.  TSV Redundancy: Architecture and Design Issues in 3-D IC , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.