Dual-Metastability Time-Competitive True Random Number Generator

The paper introduces a new concept of a true random number generator (TRNG). Most metastability-based solutions operate on the uncertainty of a logical output state of a device (flip-flop, D-latch) aimed to be resolved from an exact metastable point. However, it has been shown that the metastable point of a bistable circuit (which is practically impossible to reach) does not guarantee absolute randomness or sufficient entropy. We propose the concept of a device in which the direct proximity of the metastable point is not mandatory. In our concept the transition times of two devices are compared. Such construction is less sensitive to the proximity of the metastable point, temperature fluctuations, and power supply instabilities. The paper briefly describes the metastability phenomena in general and other known metastability-based TRNG concepts. A new concept of a dual-metastability time-competitive generator is presented, analyzed both numerically and theoretically, and verified based on the sample circuit's implementation. Empirical and statistical test results are presented.

[1]  C. E. Stroud,et al.  Metastability of CMOS master/slave flip-flops , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[2]  H. F. Li,et al.  Design of synchronisers: a review , 1989 .

[3]  Shuichi Ichikawa,et al.  FPGA Implementation of Metastability-Based True Random Number Generator , 2009, IEICE Trans. Inf. Syst..

[4]  Riccardo Rovatti,et al.  On Statistical Tests for Randomness Included in the NIST SP800-22 Test Suite and Based on the Binomial Distribution , 2012, IEEE Transactions on Information Forensics and Security.

[5]  Simon W. Moore,et al.  The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators , 2009, CHES.

[6]  Jens Horstmann,et al.  Metastability behavior of CMOS ASIC flip-flops in theory and test , 1989 .

[7]  Takayasu Sakurai Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs , 1988 .

[8]  J. McNeill,et al.  A digital-PLL-based true random number generator , 2005, Research in Microelectronics and Electronics, 2005 PhD.

[9]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[10]  Maire O'Neill,et al.  Ultra-lightweight true random number generators , 2010 .

[11]  C. Dike,et al.  Miller and noise effects in a synchronizing flip-flop , 1999 .

[12]  J. Navarro,et al.  Metastability behavior of mismatched CMOS flip-flops using state diagram analysis , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[13]  David J. Kinniment,et al.  Synchronization circuit performance , 2002 .

[14]  E.Y. Lam,et al.  FPGA-based High-speed True Random Number Generator for Cryptographic Applications , 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

[15]  Aleksander Burd Non-noise instabilities in oscilloscope trigger circuits , 2011 .

[16]  Peter Alfke Metastable Recovery in Virtex-II Pro FPGAs , 2005 .

[17]  Milos Drutarovský,et al.  New High Entropy Element for FPGA Based True Random Number Generators , 2010, CHES.

[18]  T. C. Tang Experimental studies of metastability behaviors of sub-micron CMOS ASIC flip flops , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[19]  M. Drutarovsky,et al.  A Robust Chaos-Based True Random Number Generator Embedded in Reconfigurable Switched-Capacitor Hardware , 2007, 2007 17th International Conference Radioelektronika.

[20]  J.-L. Danger,et al.  Fast True Random Generator in FPGAs , 2007, 2007 IEEE Northeast Workshop on Circuits and Systems.

[21]  J.D. Golic,et al.  New Methods for Digital Generation and Postprocessing of Random Data , 2006, IEEE Transactions on Computers.

[22]  Berk Sunar,et al.  A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks , 2007, IEEE Transactions on Computers.

[23]  Paul C. Kocher,et al.  The intel random number generator , 1999 .

[24]  Ingrid Verbauwhede,et al.  FPGA Vendor Agnostic True Random Number Generator , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[25]  Philip Heng Wai Leong,et al.  Compact FPGA-based true and pseudo random number generators , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[26]  Trevor Mudge,et al.  True Random Number Generator With a Metastability-Based Quality Control , 2008, IEEE J. Solid State Circuits.

[27]  Stephen H. Unger,et al.  Hazards, Critical Races, and Metastability , 1995, IEEE Trans. Computers.

[28]  Piotr Z. Wieczorek,et al.  Non-linear modelling of resolve time in D-latch circuits , 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

[29]  Samiha Mourad,et al.  A new model for metastability , 2002, 9th International Conference on Electronics, Circuits and Systems.

[30]  Lee-Sup Kim,et al.  Metastability of CMOS latch/flip-flop , 1990 .

[31]  R. C. Fairfield,et al.  An LSI Random Number Generator (RNG) , 1985, CRYPTO.

[32]  Riccardo Rovatti,et al.  Second-level NIST Randomness Tests for Improving Test Reliability , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[33]  Sung-il Pae,et al.  DRAM as source of randomness , 2009 .

[34]  Wayne P. Burleson,et al.  Entropy extraction in metastability-based TRNG , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[35]  Milos Drutarovský,et al.  Model of a true random number generator aimed at cryptographic applications , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[36]  Milos Drutarovský,et al.  High Performance True Random Number Generator in Altera Stratix FPLDs , 2004, FPL.